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gl850a usb 2.0 low-power hub controller datasheet revision 1.69 jul. 19, 2007 genesys logic, inc.
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 2 copyright: copyright ? 2007 genesys logic incorporated. all rights reserv ed. no part of the materials may be reproduced in any form or by any means without prio r written consent of genesys logic, inc. disclaimer: all materials are provided ?as is? without express or implied warranty of any kind. no license or right is granted under any pat ent or trademark of genesys logic inc.. genesys logic hereby disclaims all warranties and conditions in regard to materials, including all wa rranties, implied or express, of merchantability, fitness for any partic ular purpose, and non-infringement of intellectual property. in no e vent shall genesys logic be liable for any damages including, without limita tion, damages resulting from loss of information or profits. please be adv ised that the materials may contain errors or ommisions. genesys logic may make changes to the materials or to the products described therein at a ny time without notice. trademarks: is a registered trademark of genesys logic, inc. all trademarks are the properties of their respect ive owners. office: genesys logic, inc. 12f, no. 205, sec. 3, beishin rd., shindian city, taipei, taiwan tel: (886-2) 8913-1888 fax: (886-2) 6629-6168 http ://www.genesyslogic.com
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 3 revision history revision date description 1.0 03/21/2005 first release 1.50 04/21/2005 1. modify green1~4 and amber1~4, ch. 3.3, p.11 2. add maxpower describe, ch. 5.2.5, p.20 3. add ch.6.4 ?power consumption, p.23 1.51 04/25/2005 modify ?maxpoer? to ?maxpower?, table 5.1, p.20 1.52 04/26/2005 modify table3.3 pin descriptions(pself),p.11 1.60 06/20/2005 modify table 8.1 ordering information,p27 1.61 07/07/2005 1. modify pin#46 ,pin#36 ,gl850a 48pin pinout, ch3. 1,p.9 2. modify pin#61 ,pin#49 ,gl850a 64pin pinout ch3.1, p.10 3. add pin name ?ee_cs/ee_di?, hub interface,table3. 4, p.12 4. modify fosc ,table 6.1- maximum ratings,p.24 5. modify vcc ,table 6.2 ? operating ranges,p.24 1.62 09/07/2005 modify pin descriptions ,table3.3 ,p.12 1.63 09/15/2005 modify hub interface ,table3.3 pin description, p.13 1.64 12/28/2005 modify pin list and pin descriptions of ee_cs, ee_di , ee_sk, p.11~12 1.65 03/29/2006 add input voltage for digital i/o(ovcur1-4,pself,reset) pins,p.24 1.66 11/03/2006 modify 93c46 configuration, table 5.1, p.22 1.67 01/17/2007 modify table 6.1-maximum ratings, p.24 1.68 03/12/2007 modify reset# setting, ch5.2.1, p.18 1.69 07/19/2007 modify pgang/suspnd setting, ch5.2. 2, p.19
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 4 table of contents chapter 1 general description..................... .............................. 7 chapter 2 features ................................ .............................................. 8 chapter 3 pin assignment .......................... ...................................... 9 3.1 p inouts ................................................... ................................................... 9 3.2 p in l ist ................................................... ................................................. 11 3.3 p in d escriptions ................................................... ................................ 12 chapter 4 block diagram........................... ................................... 15 chapter 5 function description .................... ........................... 16 5.1 g eneral ................................................... ............................................... 16 5.2 c onfiguration and i/o s ettings ................................................... .... 18 chapter 6 electrical characteristics.............. ................. 24 6.1 m aximum r atings ................................................... .............................. 24 6.2 o perating r anges ................................................... ............................. 24 6.3 dc c haracteristics ................................................... ......................... 24 6.4 p ower c onsumption ................................................... ......................... 26 chapter 7 package dimension....................... .............................. 27 chapter 8 ordering information .................... ........................ 29
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 5 list of figures f igure 3.1 gl850a 48 p in lqfp p inout d iagram ................................................... 9 f igure 3.2 gl850a 64 p in lqfp p inout d iagram ................................................. 10 f igure 4.1 ? gl850a b lock d iagram ( single tt)................................................ .... 15 f igure 5.1 ? o perating in usb 1.1 scheme ................................................... .............. 17 f igure 5.2 ? o perating in usb 2.0 scheme ................................................... .............. 18 f igure 5.3 ? reset# (e xternal r eset ) setting and application ........................ 19 f igure 5.4 ? p ower on sequence of gl850a ............................................. ................ 19 f igure 5.5 ? t iming of pgang/suspnd strapping ................................................. 20 f igure 5.6 ? gang m ode s etting ................................................... ............................ 20 f igure 5.7 ? self/bus p ower s etting ................................................... ................... 21 f igure 5.8 ? led c onnection ................................................... ................................... 21 f igure 5.9 ? s chematics b etween gl850a and 93c46 ............................................ 23 f igure 7.1 ? gl850a 48 p in lqfp p ackage ................................................... ............ 27 f igure 7.2 ? gl850a 64 p in lqfp p ackage ................................................... ............ 28
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 6 list of tables t able 3.1 gl850a 48 p in l ist ................................................... ................................. 11 t able 3.2 gl850a 64 p in l ist ................................................... ................................ 11 t able 3.3 - p in d escriptions ................................................... ...................................... 12 t able 5.1 ? 93c46 c onfiguration ................................................... ............................ 22 t able 6.1 ? m aximum r atings ................................................... ................................... 24 t able 6.2 ? o perating r anges ................................................... .................................. 24 t able 6.3 ? dc c haracteristics e xcept usb s ignals ............................................ 24 t able 6.4 ? dc c haracteristics of usb s ignals u nder fs/ls m ode ................. 25 t able 6.5 ? dc c haracteristics of usb s ignals u nder hs m ode ...................... 25 t able 6.6 ? dc s upply c urrent ................................................... ................................ 26 t able 8.1 ? o rdering i nformation ................................................... .......................... 29
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 7 chapter 1 general description gl850a is genesys logic?s advanced version hub solu tions which fully comply with universal serial bus specification revision 2.0. gl850a embeds an 8-bit risc processor to manipulate the control/status registers and respond to the re quests from usb host. firmware of gl850a will control its general purpose i/o (gpio) to access the external eeprom and then respond to the host the customized pid and vid configured in the external eeprom. default settings in the internal mask rom is respon ded to the host without having external eerom. gl85 0a is designed for customers with much flexibility. th e more complicated settings such as pid, vid, and n umber of downstream ports settings are easily achieved by programming the external eeprom (ref. to chapter 5 ). each downstream port of gl850a supports two-color ( green/amber) status leds to indicate normal/abnorma l status. gl850a also support both individual and gan g modes (4 ports as a group) for power management. the gl850a (64-pin) is a full function solution whi ch supports both individual/gang power management modes and the two-color (green/amber) status leds. the low pin-count version gl850a (48-pin) only supports gang mode. please refer the table in the e nd of this chapter for more detail. to fully meet the cost/performance requirement, gl8 50a is a single tt hub solution for the cost requir ement. genesys logic also provides gl852 for multiple tt h ub solution to target on systems which require high er performance for full/low-speed devices, like dockin g station, embedded system ? etc.. please refer to gl852 datasheet for more detailed information. *tt (transaction translator) is the main traffic co ntrol engine in an usb 2.0 hub to handle the unbala nced traffic speed between the upstream port and the dow nstream ports. product name package type power mode led support gl850a 64lqfp individual/gang green/amber gl850a 48lqfp gang green/amber
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 8 chapter 2 features ? compliant to usb specification revision 2.0 ? 4 downstream ports ? upstream port supports both high-speed (hs) and ful l-speed (fs) traffic ? downstream ports support hs, fs, and low-speed (ls) traffic ? 1 control pipe (endpoint 0, 64-byte data payload) a nd 1 interrupt pipe (endpoint 1, 1-byte data payloa d) ? backward compatible to usb specification revision 1.1 ? on-chip 8-bit micro-processor ? risc-like architecture ? usb optimized instruction set ? dual cycle instruction execution ? performance: 6 mips @ 12mhz ? with 64-byte ram and 2k internal rom ? support customized pid, vid by reading external eep rom ? support downstream port configuration by reading ex ternal eeprom ? single transaction translator (stt) ? single tt shares the same tt control logics for all downstream port devices. this is the most cost effective solution for tt. multiple tt provides ind ividual tt control logics for each downstream port. this is a performance better choice for usb 2.0 hub . please refer to gl852 datasheet for more detailed information. ? each downstream port supports two-color status indi cator, with automatic and manual modes compliant to usb specification revision 2.0 ? support both individual and gang modes of power man agement and over-current detection for downstream ports (64-pin lqfp) ? support gang mode of power management and over-curr ent detection for downstream ports ? conform to bus power requirements ? automatic switching between self-powered and bus-po wered modes ? integrate usb 2.0 transceiver ? pll embedded with external 12 mhz crystal ? operate on 3.3 volts ? embed serial resister for usb signals and integrate pull-up resister for upstream usb signal ? improve output drivers with slew-rate control for e mi reduction ? internal power-fail detection for esd recovery ? 64/48-pin lqfp package ? applications: ? stand-alone usb hub ? pc motherboard usb hub, docking of notebook ? any compound device to support usb hub function
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 9 chapter 3 pin assignment 3.1 pinouts gl850a lqfp - 48 avdd 1 agnd 2 dm0 3 dp0 4 dm1 5 dp1 6 avdd 7 agnd 8 dm2 9 dp2 10 rref 11 avdd 12 amber2/ee_di green2/ee_do dvdd dgnd amber3 green3 nc test reset# dvdd dgnd amber4 36 35 34 33 32 31 30 29 28 27 26 25 pself 37 dgnd 38 dvdd 39 pgang/suspnd 40 ovcur1# 41 pwren1# 42 dgnd 43 dvdd 44 green1/ee_sk 45 amber1/ee_cs 46 dgnd 47 dvdd 48 green4 dp4 dm4 agnd avdd dp3 dm3 agnd avdd x2 x1 agnd 24 23 22 21 20 19 18 17 16 15 14 13 figure 3.1 gl850a 48 pin lqfp pinout diagram
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 10 figure 3.2 gl850a 64 pin lqfp pinout diagram
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 11 3.2 pin list table 3.1 gl850a 48 pin list pin# pin name type pin# pin name type pin# pin name type pin# pin name type 1 avdd p 13 agnd p 25 amber4 o 37 pself i 2 agnd p 14 x1 i 26 dgnd p 38 dgnd p 3 dm0 b 15 x2 o 27 dvdd p 39 dvdd p 4 dp0 b 16 avdd p 28 reset# i 40 pgang/ suspnd b 5 dm1 b 17 agnd p 29 test i 41 ovcur1# i 6 dp1 b 18 dm3 b 30 nc - 42 pwren1# o 7 avdd p 19 dp3 b 31 green3 o 43 dgnd p 8 agnd p 20 avdd p 32 amber3 o 44 dvdd p 9 dm2 b 21 agnd p 33 dgnd p 45 green1/ ee_sk o 10 dp2 b 22 dm4 b 34 dvdd p 46 amber1/ ee_cs o 11 rref b 23 dp4 b 35 green2/ ee_do b 47 dgnd p 12 avdd p 24 green4 o 36 amber2/ ee_di o 48 avdd p table 3.2 gl850a 64 pin list pin# pin name type pin# pin name type pin# pin name type pin# pin name type 1 agnd p 17 rref b 33 nc - 49 amber2/ ee_di o 2 nc - 18 avdd p 34 green4 o 50 pself i 3 dm0 b 19 agnd p 35 amber4 o 51 dgnd p 4 dp0 b 20 x1 i 36 dgnd p 52 dvdd p 5 nc - 21 x2 o 37 dvdd p 53 pgang/ suspnd b 6 nc - 22 avdd p 38 reset# i 54 ovcur2# i 7 nc - 23 agnd p 39 test i 55 pwren2# o 8 dm1 b 24 nc - 40 ovcur4# i 56 ovcur1# i 9 dp1 b 25 dm3 b 41 pwren4# o 57 pwren1# o 10 nc - 26 dp3 b 42 ovcur3# i 58 dgnd p 11 avdd p 27 nc - 43 pwren3# o 59 dvdd p 12 agnd p 28 avdd p 44 green3 o 60 green1/ ee_sk o 13 nc - 29 agnd p 45 amber3 o 61 amber1/ ee_cs o 14 dm2 b 30 nc - 46 dgnd p 62 dgnd p
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 12 15 dp2 b 31 dm4 b 47 dvdd p 63 avdd p 16 nc - 32 dp4 b 48 green2/ ee_do b 64 avdd p 3.3 pin descriptions table 3.3 - pin descriptions usb interface gl850a pin name 48pin# 64 pin# i/o type description dm0,dp0 3,4 3,4 b usb signals for usport dm1,dp1 5,6 8,9 b usb signals for dsport1 dm2,dp2 9,10 14,15 b usb signals for dsport2 dm3,dp3 18,19 25,26 b usb signals for dsport3 dm4,dp4 22,23 31,32 b usb signals for dsport4 rref 11 17 b a 680 % resister must be connected between rref and analog ground (agnd). note: usb signals must be carefully handled in pcb routing. for detailed information, please refer to gl850a design guideline . hub interface gl850a pin name 48pin# 64 pin# i/o type description ovcur1#~4 41 56,54, 42,40 i (pu) active low. over current indicator for dsport1~4 ovcur1# is the only over current flag for gang mode. pwren1#~4 42 57,55, 43,41 o active low. power enable output for dsport1~4 pwren1# is the only power-enable output for gang mode. green1~4 45,35, 31,24 60,48, 44,34 1,3,4: o 2: b (pd) green led indicator for dsport1~4 *green[1~2] are also used to access the external eep rom for detailed information, please refer to chapter 5 . amber1~4 46,36, 32,25 61,49, 45,35 o (pd) amber led indicator for dsport1~4 *amber[1~2] are also used to access the external ee prom ee_cs/ ee_di - - i used to access the external eeprom. for detailed information, please refer to chapter 5 . pself 37 50 i 0: gl850a is bus-powered. 1: gl850a is self-powered. pgang/ suspnd 40 53 b this pin is default put in input mode after power- on reset. individual/gang mode is strapped during this period. after the strapping period, this pin will b e set to
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 13 output mode, and then output high for normal mode. when gl850a is suspended, this pin will output low. *for detailed explanation, please see chapter 5 gang input:1, output: 0@normal, 1@suspend individual input:0, output: 1@normal, 0@suspend clock and reset interface gl850a pin name 48pin# 64pin# i/o type description x1 14 20 i 12mhz crystal clock input. x2 15 21 o 12mhz crystal clock output. reset# 28 38 i active low. external reset input, default pull high 10k % . when reset# = low, whole chip is reset to the initia l state. system interface gl850a pin name 48pin# 64 pin# i/o type description test 29 39 i (pd) 0: normal operation. 1: chip will be put in test mode. power / ground gl850a pin name 48pin# 64 pin# i/o type description avdd 1,7,12, 16,20 11,18,22, 28,64 p 3.3v analog power input for analog circuits. agnd 2,8,13, 17,21 1,12,19, 23,29 p analog ground input for analog circuits. dvdd 27,34, 39,44 37,47, 52,59 p 3.3v digital power input for digital circuits dgnd 26,33, 38, 43,47 36,46, 51,58,62 p digital ground input for digital circuits. nc 30 2,5~7, 10,13,16, 24,27,30, 33 - no connection note: analog circuits are quite sensitive to power and ground noise. pcb layout must take care the power routing and the ground plane. for detailed informat ion, please refer to gl850a design guideline . notation: type o output i input b bi-directional b/i bi-directional, default input b/o bi-directional, default output p power / ground
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 14 a analog so automatic output low when suspend pu internal pull up pd internal pull down odpu open drain with internal pull up
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 15 chapter 4 block diagram frtimer usport transceiver ram cpu control/status register utmi usport logic sie d+ d- gpio repeater repeater / tt routing logic dsport1 logic dsport2 logic dsport3 logic dsport4 logic dsport transceiver dsport dsport dsport 12mhz d+ d- led/ ovcur/ pwrenb d+ d- led/ ovcur/ pwrenb d+ d- led/ ovcur/ pwrenb d+ d- led/ ovcur/ pwrenb tt (transaction translator) pll x40, x10 transceiver transceiver transceiver rom figure 4.1 ? gl850a block diagram (single tt)
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 16 chapter 5 function description 5.1 general 5.1.1 usport transceiver usport (upstream port) transceiver is the analog ci rcuit that supports both full-speed and high-speed electrical characteristics defined in chapter 7 of usb specification revision 2.0 . usport transceiver will operate in full-speed electrical signaling when gl8 50a is plugged into a 1.1 host/hub. usport transcei ver will operate in high-speed electrical signaling whe n gl850a is plugged into a 2.0 host/hub. 5.1.2 pll (phase lock loop) gl850a contains a 40x pll. pll generates the clock sources for the whole chip. the generated clocks ar e proven quite accurate that help in generating high speed signal without jitter. 5.1.3 frtimer this module implements hub (micro)frame timer. the (micro)frame timer is derived from the hub?s local clock and is synchronized to the host (micro)frame period by the host generated start of (micro)frame (sof). frtimer keeps tracking the host?s sof such t hat gl850a is always safely synchronized to the host. the functionality of frtimer is described in section 11.2 of usb specification revision 2.0 . 5.1.4 c c is the micro-processor unit of gl850a. it is an 8 -bit risc processor with 2k rom and 64 bytes ram. it operates at 6mips of 12mhz clock to decode the u sb command issued from host and then prepares the data to respond to the host. in addition, c can handle gpio (general purpose i/o) settings an d reading content of eeprom to support high flexibility for c ustomers of different configurations of hub. these configurations include self/bus power mode setting, individual/gang mode setting, downstream port numb er setting, device removable/non-removable setting, an d pid/vid setting. 5.1.5 utmi (usb 2.0 transceiver macrocell interface ) utmi handles the low level usb protocol and signali ng. it?s designed based on the intel?s utmi specification 1.01. the major functions of utmi log ic are to handle the data and clock recovery, nrzi encoding/decoding, bit stuffing /de-stuffing, suppo rting usb 2.0 test modes, and serial/parallel conve rsion. 5.1.6 usport logic usport implements the upstream port logic defined i n section 11.6 of usb specification revision 2.0 . it mainly manipulates traffics in the upstream directi on. the main functions include the state machines o f receiver and transmitter, interfaces between utmi a nd sie, and traffic control to/from the repeater and tt. 5.1.7 sie (serial interface engine) sie handles the usb protocol defined in chapter 8 o f usb specification revision 2.0 . it co-works with c to play the role of the hub kernel. the main functi ons of sie include the state machine of usb protoco l flow, crc check, pid error check, and timeout check . unlike usb 1.1, bit stuffing/de-stuffing is implemented in utmi, not in sie. 5.1.8 control/status register control/status register is the interface register b etween hardware and firmware. this register contain s the information necessary to control endpoint0 and endp oint1 pipelines. through the firmware based architecture, gl850a possesses higher flexibility t o control the usb protocol easily and correctly. 5.1.9 repeater repeater logic implements the control logic defined in section 11.4 and section 11.7 of usb specification revision 2.0 . repeater controls the traffic flow when upstream port and downstream port are signaling in the same speed. in addition, repeater will gener ate internal resume signal whenever a wakeup event is issued under the situation that hub is globally suspended.
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 17 5.1.10. tt (transaction translator) tt implements the control logic defined in section 11.14 ~ 11.22 of usb specification revision 2.0 . tt basically handles the unbalanced traffic speed betw een the usport (operating in hs) and dsports (operating in fs/ls) of hub. gl850a adopts the sing le tt architecture to provide the most cost effecti ve solution. single tt shares the same buffer control module for each downstream port. gl852 adopts multiple tt architecture to provide the most perfor mance effective solution. multiple tt provides cont rol logics for each downstream port respectively. pleas e refer to gl852 datasheet for more detailed information. 5.1.11 repeater/tt routing logic repeater and tt are the major traffic control machi nes in the usb 2.0 hub. under situation that usport and dsport are signaling in the same speed, repeater/tt routing logic switches the traffic channel to the repeater. under situation that uspor t is in the high speed signaling and dsport is in the full/low speed signaling, repeater/tt routing l ogic switches the traffic channel to the tt. 5.1.11.1 connected to 1.1 host/hub if an usb 2.0 hub is connected to the downstream po rt of an usb 1.1 host/hub, it will operate in usb 1 .1 mode. for an usb 1.1 hub, both upstream direction t raffic and downstream direction traffic are passing through repeater. that is, the repeater/tt routing logic will route the traffic channel to the repeater. usb1.1 host/hub repeater tt dsport operating in fs/ls signaling usportoperating in fs signaling traffic channel is routed to repeater figure 5.1 ? operating in usb 1.1 scheme 5.1.11.2 connected to usb 2.0 host/hub if an usb 2.0 hub is connected to an usb 2.0 host/h ub, it will operate in usb 2.0 mode. the upstream p ort signaling is in high speed with bandwidth of 480 mb ps under this environment. the traffic channel will then be routed to the repeater when the device conn ected to the downstream port is signaling also in high speed. on the other hand, the traffic channel will then be routed to tt when the device connected to the downstream port is signaling in full/low speed.
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 18 usb2.0 host/hub repeater tt usportoperating in hs signaling hs vs. fs/ls: traffic channel is routed to tt hs vs. hs: traffic channel is routed to repeater dsport operating in hs signaling dsport operating in fs/ls signaling figure 5.2 ? operating in usb 2.0 scheme 5.12 dsport logic dsport (downstream port) logic implements the contr ol logic defined in section 11.5 of usb specification revision 2.0 . it mainly manipulates the state machine, the conn ection/disconnection detection, over current detection and power enable control, and the status led control of the downstream port. besides, it als o output the control signals to the dsport transceive r. 5.13 dsport transceiver dsport transceiver is the analog circuit that suppo rts high-speed, full-speed, and low-speed electrica l characteristics defined in chapter 7 of usb specification revision 2.0 . in addition, each dsport transceiver accurately controls its own squelch lev el to detect the detachment and attachment of devic es. 5.2 configuration and i/o settings 5.2.1 reset# setting gl850a integrates in the pull-up 1.5k % resister of the upstream port. when reset# is enab led, the internal 1.5k % pull-up resister will be disconnected to the 3.3v power. to meet the requirement (p.141) of the usb 2.0 specification, pull-up resister should be disconnected while lacking of usb cable power (vbus). therefore, we suggest designing the reset# circuit as following figure to meet the requirement mentioned above.
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 19 avdd (3.3v) c r vbus (5v) reset# 1.5k ohm dp0 inside gl850a on pcb 33 ohm r figure 5.3 ? reset# (external reset) se tting and application gl850a internally contains a power on reset circuit . the power on sequence is depicted in the next pic ture. to fully control the reset process of gl850a, we su ggest the reset time applied in the external reset circuit should longer than that of the internal reset circu it. P 2.7 s internal reset external reset power good voltage, 2.5~2.8v vcc(3.3v) figure 5.4 ? power on sequence of gl850a 5.2.2 pgang/suspnd setting to save pin count, gl850a uses the same pin to deci de individual/gang mode as well as to output the suspend flag. the individual/gang mode is decided w ithin 20us after power on reset. then, about 50ms l ater, this pin is changed to output mode. gl850a outputs the suspend flag once it is globally suspended. for individual mode, a pull low resister greater than 1 00k % should be placed. for gang mode, a pull high resister greater than 100k % should be placed. in figure 5.6, we also depict th e suspend led indicator schematics. it should be noticed that the polarity of led must be followed, otherwise the suspend curr ent will be over spec limitation (2.5ma).
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 20 reset# gang_ctl 50ms input mode, strapping to decide individual or gang mode output mode, indicating gl850a is in normal mode or suspend mode figure 5.5 ? timing of pgang/suspnd strapping dvdd(3.3v) 100k ohm 100k ohm dvdd(3.3v) suspend led indicator suspend led indicator gand mode individual mode "0": individual mode "1": gang mode suspndo gang_ctl inside gl850a on pcb pgang figure 5.6 ? gang mode setting 5.2.3 self/bus power setting gl850a can operate under bus power and conform to t he power consumption limitation completely (suspend current < 2.5 ma, normal operation current < 100 ma). by setting pself, gl850a can be configured as a bus-power or a self-power hub.
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 21 1: power self 0: power bus pself inside gl850a on pcb figure 5.7 ? self/bus power setting 5.2.4 led connections gl850a controls the led lighting according to the f low defined in section 11.5.3 of universal serial bus specification revision2.0 . both manual mode and automatic mode are supported in gl850a. when gl850a is globally suspended, gl850a will turn off the led to save power. amber/green inside gl850a on pcb dgnd led figure 5.8 ? led connection 5.2.5 eeprom setting gl850a replies to host commands by the default sett ings in the internal rom. gl850a also offers the ability to reply to the host according to the setti ngs in the external eeprom(93c46). the following ta ble shows the configuration of 93c46.
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 22 table 5.1 ? 93c46 configuration unit: byte 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00h vid_l vid_h pid_l pid_h chksum ff device removable port number maxpower ff ff ff ff ff ff ff 10h vendor length start 20h vendor string (asc ii code) 30h end 40h product length start 50h product string(asc ii code) 60h end 70h serial number length start serial number string(asc ii code) end note: 1. vid_h/vid_l: high/low byte of vid value 2. pid_h/pid_l: high/low byte of pid value 3. chksum: chksum must equal to vid_h + vid_l + p id_h + pid_l + 1,otherwise firmware will ignore the eeprom settings. 4. port_no: port number, value must be 1~4. 5. maxpower : describe the maximum power consumpt ion, range=0ma~500ma . value -> 00h~fah (unit = 2ma) 6. device removalbe: - - - port4 removable port3 removable port2 removable port1 removable - 0: device attached to this port is removable. 1: device attached to this port is non-removable. 7. vendor length: offset 10h contains the length of the vendor string. values of vendor string is contained from 11h~3fh. 8. product length: offset 40h contains the length o f product string. values of product string is contained from 41h~6fh. 9. serial number length: offset 70h contains the va lue of serial number string. values of serial number string is contained after offset 71h.
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 23 the schematics between gl850a and 93c46 is depicted in the following figures: vcc nc nc gnd cs sk di do ee_cs ee_sk ee_di ee_do 93c46 dvdd figure 5.9 ? schematics between gl850a and 93c46 gl850a firstly verifies the check sum after power o n reset. if the check sum is correct, gl850a will t ake the configuration of 93c46 as part of the descripto r contents. to prevent the content of 93c46 from be ing over-written, amber led will be disabled when 93c46 exists.
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 24 chapter 6 electrical characteristics 6.1 maximum ratings table 6.1 ? maximum ratings symbol parameter min. max. unit v cc power supply -0.5 +3.6 v v in input voltage for digital i/o(ee_do) pins -0.5 +3. 6 v v in input voltage for digital i/o(ovcur1-4,pself,reset ) pins -0.5 +5.25 v v inusb input voltage for usb signal (dp, dm) pins -0.5 +3. 6 v t s storage temperature under bias -60 +100 o c f osc frequency 12 mhz 0.05% 6.2 operating ranges table 6.2 ? operating ranges symbol parameter min. typ. max. unit v cc power supply 3.0 3.3 3.6 v v ind input voltage for digital i/o pins -0.5 3.3 3.6 v v inusb input voltage for usb signal (dp, dm) pins 0.5 3.3 3.6 v t a ambient temperature 0 - 70 o c 6.3 dc characteristics table 6.3 ? dc characteristics except usb signals symbol parameter min. typ. max. unit p d power dissipation 70 - 180 ma v dd power supply voltage 3 3.3 3.6 v v il low level input voltage - - 0.9 v v ih high level input voltage 2.0 - - v v tlh low to high threshold voltage 1.36 1.48 1.62 v v thl high to low threshold voltage 1.36 1.48 1.62 v v ol low level output voltage when i ol =8ma - - 0.4 v v oh high level output voltage when i oh =8ma 2.4 - - v i olk leakage current for pads with internal pull up or p ull down resistor - - 30 a r dn pad internal pull down resister 81k 103k 181k % r up pad internal pull up resister 81k 103k 181k %
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 25 table 6.4 ? dc characteristics of usb signals under fs/ls mode symbol parameter min. typ. max. unit v ol dpf/dmf static output low(r l of 1.5k to 3.6v ) 0 - 0.3 v v oh dpf/dmf static output high (r l of 15k to gnd ) 2.8 - 3.6 v v di differential input sensitivity 0.2 - - v v cm differential common mode range 0.8 - 2.5 v v se single-ended receiver threshold 0.2 - - v c in transceiver capacitance - - 20 pf i lo hi-z state data line leakage -10 - +10 a z drv driver output resistance 28 - 43 % table 6.5 ? dc characteristics of usb signals under hs mode symbol parameter min. typ. max. unit v ol dph/dmh static output low(r l of 1.5k to 3.6v ) - - 0.1 v c in transceiver capacitance 4 4.5 5 pf i lo hi-z state data line leakage -5 0 +5 a z drv driver output resistance for usb 2.0 hs 48 45 42 %
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 26 6.4 power consumption table 6.6 ? dc supply current condition symbol active ports host device typ. unit i susp suspend 540/800 *1 a f *2 f 93 ma h h 180 ma 4 h f 115 ma f f 91 ma h h 160 ma 3 h f 111 ma f f 89 ma h h 140 ma 2 h f 106 ma f f 87 ma h h 115 ma 1 h f 102 ma f 80 ma i cc no active h 95 ma *1: 48/64-pin package types *2: f: full-speed, h: high-speed
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 27 chapter 7 package dimension control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d e d1 e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 9.00 basic 9.00 basic 7.00 basic 7.00 basic 0.354 basic 0.354 basic 0.276 basic 0.276 basic 0.05 1.35 1.40 1.60 0.15 1.45 0 0 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 0 0 11 11 3.5 12 12 7 13 13 0.063 0.006 0.057 0.055 0.002 0.053 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.50 basic 5.50 basic 5.50 basic 0.020 basic 0.217 basic 0.217 basic 1.00 ref 0.039 ref 0.09 0.45 0.20 0.17 0.60 0.20 0.20 0.75 0.27 0.004 0.018 0.008 0.007 0.024 0.008 0.008 0.030 0.011 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. 1 24 25 36 37 48 12 13 seating plane e b 4x 4x e e 1 e 2 a a b d c aaa b a d h bbb ddd m c b a s s d b d1 d2 d d a a2 a1 0 . 0 5 s l 1 c 0 1 - 0 - c c ccc gage plane r1 r2 0.25mm s l 0 3 - 0 2 - h gl850a aaaaaaagaa ywwxxxxxxxx date code lot code internal no. version no. n : normal package g : green package figure 7.1 ? gl850a 48 pin lqfp package
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 28 16 control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d d1 e e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 12.00 basic 12.00 basic 10.00 basic 10.00 basic 0.472 basic 0.472 basic 0.393 basic 0.393 basic 0.05 1.35 1.40 1.60 0.15 1.45 00 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 00 11 11 3.5 12 12 7 13 13 0.063 0.006 0.057 0.055 0.002 0.053 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.50 basic 7.50 basic 7.50 basic 0.020 basic 0.295 basic 0.295 basic 1.00 ref 0.039 ref 0.09 0.45 0.20 0.17 0.60 0.20 0.20 0.75 0.27 0.004 0.018 0.008 0.007 0.024 0.008 0.008 0.030 0.011 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. seating plane e b 4x 4x 64 1 17 32 33 48 49 gage plane r1 r2 0.25mm s l 0 3 - 0 2 - h e e 1 e 2 a a b d c aaa b a d h bbb ddd m c b a s s d b d1 d2 d d a a2 a1 0 . 0 5 s l 1 c 0 1 - 0 - c c ccc gl850a aaaaaaagaa ywwxxxxxxxx date code lot code internalno . version no. n : normal package g : green package figure 7.2 ? gl850a 64 pin lqfp package
gl850a usb 2.0 low-power hub controller ?2000-2007 genesys logic inc. - all rights reserved . page 29 chapter 8 ordering information table 8.1 ? ordering information part number package normal/green version status gl850a-msnxx 64-pin lqfp normal package xx available gl850a-mnnxx 48-pin lqfp normal package xx available GL850A-MSGXX 64-pin lqfp green package xx available gl850a-mngxx 48-pin lqfp green package xx available

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